This invention relates to semiconductor device processing, and more particularly, to latch-up prevention and increased breakdown voltage in SOI devices.
Circuits and devices built in SOI substrates have been shown to have many advantages over identical circuits built in bulk silicon substrates. SOI (silicon-on-insulator) technology has been touted as a promising approach for fabricating advanced integrated circuits because of its faster speed and improved radiation tolerance. However, one of the disadvantages of SOI devices is the parasitic bipolar induced latch-up/breakdown voltage, which severely limits the maximum power supply voltage at which SOI circuits and devices can operate. When the parasitic device turns on, the SOI device cannot be switched off by changing its gate bias. This single transistor latch-up also manifests itself as a very low breakdown voltage. The SOI device self latch-up effect is caused by a positive feedback mechanism generated by the steady-state balancing between the minority and majority carriers in the body of the transistor. For a given gate voltage, as the drain voltage is increased, the electric field at the body/drain junction becomes high enough so that electron/hole pairs are generated by impact ionization. The majority carriers (carriers of the same dopant type as the source and drain) are collected at the drain while minority carriers travel into the body of the transistor. In SOI devices, the body of the transistor is separated from the substrate by a buried oxide. The minority carriers thus collect in the body of the transistor. At sufficiently high drain bias, the concentration of minority carriers in the body disturbs the normal steady state potential of the body. To compensate, majority carriers are injected from the source. These carriers then diffuse to the high field region of the drain/body junction, creating even more electron/hole pairs by impact ionization, and cause a run-away current in the device.
Several approaches have been discussed in the known art for increasing the voltage at the drain for onset of the device self latch-up/breakdown effect. The known approaches are based on reducing the drain electric field for a given drain bias (LDD approaches) or adding an extra contact to the body of the transistor to keep it at a constant potential and to act as a sink for the excess carriers (body tie approaches).
In the body tie approach, either an extra contact is attached to the body of the transistor to keep the voltage potential from floating, or highly doped straps are used to short the body to the source. However, body ties are useful only for thick-film SOI devices. As the film becomes thinner, the sheet resistance of the body increases, and the body tie collects a lower percentage of the excess current. As a result, extra ties/straps are needed, greatly increasing the required device area. In addition, implementing body ties requires significant design changes from bulk silicon transistor technology. Thus, circuits implementing body ties must be designed for SOI from the start, thereby increasing cost.
The LDD approach aims to decrease the electric field at the body/drain junction by reducing the dopant gradient (from the very highly doped drain to the low doped body) in this region. This is accomplished by the use of a spacer to explicitly separate the drain from the body. An additional implant is used to decrease the resistance of the spacer region. This approach can be used to easily increase the operating voltage. However, a price is paid in terms of slower circuit speed. It is difficult to optimize the circuit speed versus the maximum operating voltage. In addition, the LDD process requires many process steps to be added to the transistor fabrication process.
Another approach is to reduce the lifetime of minority carriers in the transistor body. When carriers quickly recombine, a larger influx of carriers is needed to disturb the body potential sufficiently to induce the positive feedback mechanism. Thus, the voltage at which the positive feedback mechanism occurs is increased. However, it is difficult to decrease the recombination lifetime without increasing the generation lifetime. The generation lifetime refers to the generation of carriers by thermal effects. Thermally generated carriers contribute to the off-state device leakage. As devices are made with shorter gates, shorter recombination lifetimes are required to increase the maximum drain voltage. However, the generation lifetime decreases proportionally, so that the submicron devices would be excessively leaky. In addition, the minimum acceptable leakage decreases as devices are shrunk.
What is needed is a method whereby the operating voltage at which the latch-up occurs is significantly increased thus allowing circuit operation at reasonable power supply voltages.